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ISL6596
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F SW ), the output drive impedance, the
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the SO8 package is approximately 800mW at room
temperature, while the power dissipation capacity in the DFN
package, with an exposed heat escape pad, is much higher.
See “Layout Considerations” on page 9 for thermal transfer
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R G1 and R G2 , should be a short to avoid
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R GI1 and R GI2 ) of
MOSFETs. Figures 3 and 4 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as:
P DR = P DR_UP + P DR_LOW + I Q ? VCC
? R HI1 R LO1 ? P Qg_Q1
2
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation
is used to ensure safe operation at the desired frequency for
? R HI2 R LO2 ? P Qg_Q2
2
(EQ. 4)
R EXT2 = R G1 + -------------
N
R EXT2 = R G2 + -------------
N
the selected MOSFETs. The total gate drive power losses
due to the gate charge of MOSFETs and the driver ’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively:
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
VCC
R GI1
Q1
BOOT
R GI2
Q2
D
P Qg_Q1 = ---------------------------------- ? F SW ? N Q1
Q G1 ? VCC 2
V GS1
(EQ. 2)
R HI1
G
C GD
C DS
P Qg_Q2 = ---------------------------------- ? F SW ? N Q2
Q G2 ? VCC 2
V GS2
R LO1
UGATE
R G1
R GI1
C GS
S
Q1
I VCC = ? ------------------------------ + ------------------------------ ? ? VCC ? F SW + I Q
? Q G1 ? N Q1 Q G2 ? N Q2 ?
? V GS1 V GS2 ?
(EQ. 3)
PHASE
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
where the gate charge (Q G1 and Q G2 ) is defined at a
particular gate to source voltage (V GS1 and V GS2 ) in the
VCC
D
corresponding MOSFET datasheet; I Q is the driver ’s total
quiescent current with no load at both drive outputs; N Q1
and N Q2 are the number of upper and lower MOSFETs,
respectively. The I Q V CC product is the quiescent power of
R HI2
R LO2
LGATE
G
R G2
C GD
R GI2
C DS
the driver without capacitive load and is typically negligible.
GND
C GS
S
Q2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
8
FN9240.1
January 22, 2010
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